1. Field of the Invention
The present invention relates to the field of processor architecture and, more particularly, to a technique for renaming segment registers, so that segmentation instructions which use or modify segment registers can be processed by a processor non-serially.
2. Background of the Related Art
The concepts of a processor, such as the processors utilized in the current generation of desktop and laptop computers and workstations, are known in the art. The term microprocessor has been generally attributed to these types of processors. These processors typically operate implementing one of several processor architectures known in the computer industry. One of the more well-known processor family is the x86 processor family. The x86 processor family employs a processor architecture commonly referred to as the Intel Architecture and processors manufactured by Intel Corporation implement this architecture.
A processor operates by responding to program instructions, which are written by a programmer and coded for a particular protocol. These program instructions are generally compiled, assembled, translated, decoded, etc., before being placed in a form for execution by the processor's execution unit. Thus, a processor receives a given program instruction and responds to it based on the particular processor architecture. Once a given program instruction is received and decoded by the processor, micro-operation instructions are generated by the utilization of the processor microcode. The micro-operations (known as uops) perform the necessary internal operations so that execution signals are generated for executing the program instruction by the processor's execution unit(s).
The instructions take many forms, including operations to manipulate data, as well as operating on the data. For example, load, store and move instructions manipulate data, while add and multiply instructions operate on data. In order to access and move the data, the locations of the data must be identified. The data can reside in a number of locations as well. Accordingly, an addressing scheme is utilized to address and identify the resident location of the information (which can be data, instructions or other information) being sought.
A variety of addressing schemes are known in the art and one particular addressing scheme employs the use of segments to address memory. For example, processors based on the Intel Architecture utilize segmentation. Segmentation is a technique of dividing memory into a number of partitions (segments), so that a segment addressing scheme can be used as a form of logical addressing. The processor then generates a linear address, based on the segment address provided. Segmentation is distinct from the generation of the actual physical address. Techniques for segmenting the physical memory space are known in the art and one scheme is described in U.S. Pat. No. 4,972,338.
With the Intel Architecture, a set of general purpose registers are available to the execution unit for temporary storage of information. The program instructions identify architectural registers, commonly known as registers EAX, EBX, etc., for use in the temporary storage of information when performing the instructions. When the uops are completed, the final result is available as the instruction is retired. Then, this result (which is regarded as a valid architectural or committed value) can be utilized by subsequent instruction(s). Where instructions are actually executed in a sequential order as the program order, providing a one-for-one physical register structure for each of the required architectural registers is sufficient for the proper operation of the processor.
However, current generation superscalar processors operate on more than one instruction at a time and the instruction processing cycle implements a considerably deep pipeline. Furthermore, many of these superscalar processors also perform instruction operations out of order from the program order, so that the data dependencies become critical for many of the operations.
The data dependencies can be actual (true) dependencies or false dependencies. A true dependency occurs when a sequence of register operations must occur in order. For example, one operation may move a data into a register and a second operation may add a value to a stored value in the register and then store the final sum in that same register. In this instance, order in which this sequence is executed is critical. An example of a false dependency is the case when two separate operations attempt to utilize a given register, but where the operations are not inter-related. For example, one instruction may place a first value in the architectural register ECX, while a second instruction may also place a second value into ECX. The two operations do not depend on one another, but present a conflict when both instructions are being processed simultaneously. In this instance, the order of the operation is not critical, but the dependency still exists.
The earlier processors implementing the Intel Architecture were severely constrained in the availability of general purpose registers, causing compilers to reuse these registers heavily as temporary storage spaces. The dependencies limited the efficiency of the processors to perform superscalar operations. In order to alleviate this problem and to improve the processing efficiency, a technique has been developed to increase the availability of the general purpose architectural registers. One such technique is described in U.S. Pat. No. 5,548,776. The technique of renaming integer and floating point registers allows for the logical architectural registers to be mapped into a larger physical register space. The mapping is done at the execution time and the reverse mapping is done at retirement time.
A newer generation of processors have now implemented the renaming of general purpose registers to enhance performance and efficiency. However, the newer processors did not extend the renaming technique to the segment registers that are used for memory operations. Typically, programmers view the memory space as one large unsegmented space and generally with today's processors operating at 32-bits or higher, the amount of memory space available for access is sufficiently large. For a 32-bit system, 4 G of memory space is available for addressing. Thus, programmers tend to load the segment registers once and rarely reload them. However, if the instruction requires the segment registers to be reloaded, a significant performance loss is experienced due to the constraints placed on superscalar operations.
The more recent program codes designed within the 32-bit operating system can take into account the sizable memory space available. However, processors operating on the Intel Architecture are still capable of executing earlier 16-bit codes. In 16-bit code, segment registers are reloaded much more frequently, since the available memory space in 16 bits for addressing is 64 K. The segment registers are reloaded due to this limited size and also due to the practice of using segments as pointers to execute far control transfers. Thus, the 32-bit superscalar processors are significantly constrained when executing the older 16-bit programs.
The present invention improves the superscalar efficiency of executing older instructions which require more frequent reloading of segment registers. The efficiency is improved by making available more internal segment registers and providing a scheme of renaming to map into these physical registers. The invention is applicable to instructions which use or modify segment registers.